Multisim version 9 lets you run an AC analysis, and use cursors to measure bandwidth, just like you would in the lab. I am trying to replicate a design used in 'Design with Operational Amplifiers and Analog Integrated Circuits' by Sergio Franco in Figure 4.33 using Ideal components, where the component values have been worked out in Example 4.13 for f_c = 1kHz at a f_ck = 100kHz and providing the following capacitor values:Ĭ_Ri = C_Ro = C_0 = 1pF, C_C1 = C_C5 = 9.84pF, C_L2 = C_L4 = 25.75pF, and C_C3 = 31.83pF. View attachment 5th Order Butterworth - Transient 10kHz.pdfįor reference, here are my clock pulses (clk_phi and clk_phi_bar): View attachment 5th Order Butterworth - Transient 1kHz - 2.pdfīut then 10kHz, it completely disappears: View attachment 5th Order Butterworth - Transient 100Hz.pdfĪnd the Transient 1kHz is starting to go wrong: The Transient 100Hz looks somewhat reasonable, though it is clipping on the negative swing: View attachment SC 5th Order Butterworth - Bode.pdf The resulting Bode Plot is nothing like a LPF: View attachment SC 5th Order Butterworth - Circuit - Inverting Switch Block 2.pdf View attachment SC 5th Order Butterworth - Circuit - Inverting Switch Block.pdf With the heirachal inverting blocks implemented like so: View attachment SC 5th Order Butterworth - Circuit.pdf The circuit looks like so (note all components are Ideal): You can also attach a bode analyzer to your circuit, and use cursors that way.

View attachment SC 5th Order Butterworth - Clock.pdfĬan Switched Capacitor circuits be simulated in NI Multisim 13.0?Īs it is, I had a convergence problem and needed to relax ABSTOL to 1e-008A and VNTOL to 0.0001V in order to simulate the results. In the OUT portion of the file, plan to plot S 11 on a grid and Smith charts. Run an open-loop Bode plot at full load, lowest input 2. Someone had mentioned that because the convergence is being done at specific points in time, that a switched capacitor system might not be able to simulate correctly, and especially wouldn't bode plot correctly.Įventually I want to implement this circuit topology with a 7th Order Butterworth and a clock that is upwards of 10MHz, but for the present, I would be satisfied with just getting this circuit to work as expected. widths (approx 100nm) usually not a design issue Bode plot (frequency vs. Identify the excess/deficiency of gain at the selected cross over 3. Place a double zero at f 0, a pole at the ESR zero and a pole at F sw/2 4.

Bode plot multisim decade